The present invention relates to a method for fabricating a highly-integrated semiconductor memory device, and more specifically, to a semiconductor memory device with a buried gate structure with improved operation characteristics, and a method for fabricating the same.
A common semiconductor memory device includes a plurality of unit cells each of which has a capacitor and a transistor. The capacitor temporarily stores data, and the transistor transfers data between a bit line and a capacitor in response to a control signal (which is applied to a word line) by using a semiconductor property that electrical conductivity varies according to environments. The transistor has three regions: a gate, a source, and a drain. Electric charges move between the source and the drain in response to a control signal which is applied to the gate. The electric charges move through the channel formed between the source and the drain.
In forming a general transistor, a gate is formed on a semiconductor substrate, and impurities are doped into the substrate on both sides of the gate to form a source and a drain. To meet requirements for enhanced data storage capacity and integration in a semiconductor memory device, unit cell size needs to be smaller. This decreases the design rule for the capacitor and the transistor. As a result, a channel length becomes shorter, causing a short channel effect and a drain induced barrier lowering (DIBL) effect which may degrade the operational reliability of a semiconductor memory device. Those phenomena caused by the reduction of the channel length may be prevented by maintaining a threshold voltage so that a cell transistor operates normally. To this end, the doping concentration of impurities in the channel region has been increased as a channel length of a transistor gets shorter.
In sub-100 nm design rule, however, the increase of the doping concentration in the channel region causes an electric field increase in a storage node (SN) junction, which may degrade refresh characteristics of the semiconductor memory device. In order to prevent the degradation of refresh characteristics, there has been proposed a cell transistor with a three-dimensional channel structure in which a channel is elongated in a vertical direction so that a channel length of a cell transistor is maintained even though the design rule is reduced. Therefore, even when the channel width in a horizontal direction is short, the doping concentration may be reduced as much as the channel length secured in a vertical direction, thereby preventing the degradation of refresh characteristics.
Meanwhile, as the integration density of a semiconductor memory device becomes higher, the distance between a word line and a bit line connected to a cell transistor becomes smaller. For this reason, a parasitic capacitance increases, and an operational margin of a sense amplifier for amplifying data transferred through a bit line gets worse. Hence, the operational reliability of a semiconductor memory device may be fatally affected. To reduce a parasitic capacitance between a bit line and a word line, there has been proposed a buried gate structure in which a word line, i.e., a gate of a cell transistor, is formed recessed in a semiconductor substrate. In forming the buried gate structure, a recess formed in a semiconductor substrate is filled with a conductive material, and an insulating layer is formed to cover the conductive material, so that a gate is buried within the semiconductor substrate. In this way, a gate may be further electrically isolated from a bit line formed on a semiconductor substrate where a source and a drain are formed.
FIGS. 1a to 1e are cross-sectional views illustrating a method for fabricating a semiconductor device with a general buried gate structure.
Referring to FIG. 1a, a pad oxide layer 101 and a pad nitride layer 102 as insulating layers are sequentially deposited on a semiconductor substrate 100. Using a shallow trench isolation (STI) process, an isolation layer 103 is formed to define an active region in the semiconductor substrate 100.
Referring to FIG. 1b, an etch process using a recess gate mask is performed to form recesses 104 inside the active region and the isolation layer 103. Two recesses 104 are formed in the active region, and one recess 104 is formed inside the isolation layer 103.
Referring to FIG. 1c, a gate oxidation process is performed over a resulting structure where the recesses 104 are formed, thereby obtaining a gate oxide layer 107 on the surface of each recess 104. A conductive layer 105 is deposited with a predetermined thickness to fill the recess 104. In this case, since the recess 104 is filled with a metal material and not polysilicon, a threshold voltage margin of the gate may be improved because of the difference in electric charge movement between metal and silicon. Then, a chemical mechanical polishing (CMP) process is performed to planarize the conductive layer 105 until the upper portion of the pad nitride layer 102 is exposed.
Referring to FIG. 1d, an etch-back process using a difference of etch selectivity between the insulating layers 101 and 102 and the conductive layer 105 is performed to remove a predetermined upper portion of the conductive layer 105 buried within the recess 104, thereby forming a gate 105a. 
Referring to FIG. 1e, a capping oxide layer 106 is deposited on the recess over the gate 105a and the semiconductor substrate 100, and a planarization process is performed on a resulting structure. In this way, a buried gate structure 105b including the gate 105a and the capping oxide layer 106 is completed.
In recent years, a buried gate structure of the semiconductor memory device has been formed using a metal gate, instead of an N+ poly gate. Since the metal gate has a higher work function than the N+ poly gate, a higher electric field is applied to the gate oxide layer. This causes an increase of gate-induced-drain-leakage (GIDL) and thus degrades the refresh characteristic of the semiconductor memory device.
FIG. 2 is a scanning electron microscope (SEM) image explaining a GIDL occurrence principle and a GIDL occurrence region in a general buried gate structure with a metal gate.
As illustrated in FIG. 2, as an electric field applied to a gate oxide layer increases in a region where the gate is overlapped with a storage node contact region formed on a lateral side of a buried gate, the occurrence of GIDL increases in the corresponding region, resulting in degradation in the refresh characteristic of the semiconductor memory device. Meanwhile, if the metal layer is etched excessively in order to reduce the region where the gate is overlapped with the storage node contact region, a channel length is reduced and thus the concentration of a channel dose must be increased. The concentration of the channel dose has been increased in order to compensate the channel length that is reduced as the semiconductor memory device is highly integrated. Under those circumstances, further increase of the channel dose by excessive etching of the metal layer may cause an increase of GIDL occurrence and degrade the refresh characteristic of the semiconductor memory device.